Along with requirements of tiny and light electronic products, semiconductor packages serving as central components for the electronic products are gradually becoming miniaturized. Chip scale package (CSP) which is one sort of miniaturized semiconductor packages is characterized that the size of such package is equivalent to or about 1.2 times bigger than that of the chip.
Furthermore, in addition to miniaturization for the semiconductor packages, high integration and the number of input/output connections (I/O connections) for electrically connecting external devices such as circuit boards have to be improved to achieve high electrical performance and high speed for the electronic products. Generally, a maximum number of bond pads are provided on an active surface of the chip to improve the number of the input/output connections. However, the number of the bond pads provided on the chip is limited by an area of the active surface and pitches between the bond pads. For more input/output connections to be further provided on the limited area, a wafer level package, such as a wafer level chip scale package (Wafer level CSP), is proposed.
Redistribution layer technology (RDL) is employed in the wafer level package, in which a dielectric layer formed on the active surface of the chip is provided with openings to expose the bond pad located on the active surface. Then, a plurality of conductive traces is provided on the dielectric layer, such that one end of each of the conductive traces electrically connects the bond pad located on the chip whereas the other end forms a contact. A solder mask layer is further disposed on the dielectric layer for covering the conductive trace and the bond pad. Finally, a plurality of openings is formed within the solder mask layer to expose the corresponding contact of the conductive trace for connecting a solder ball. Such build-up layer fabricated using the redistribution layer technology is capable of efficiently improving the number of the input/output connections for electrically connecting the chip and external devices. However, it is still restricted by the limited area of the active surface of the chip.
Again, in order to further improve the number of the input/output connections for electrically connecting the chip and the external devices, researches have focused on ways to fan out a layout boundary of the input/output connections to areas outside the active surface of the chip. Referring to FIG. 7, U.S. Pat. No. 6,271,469 has disclosed a packaging technology that fabricates build-up layers on an encapsulated chip that has an expanded area larger than the chip. In a semiconductor package 6, a chip 60 is encapsulated with an encapsulating material 62 formed by a molding process, by which an active surface 602 of the chip 60 exposes from a surface 622 of the encapsulating material 62 after encapsulation. A build-up layer 64 (consisting of a dielectric layer 642, conductive traces 644 and a solder mask layer 646) is disposed over the active surface 602 of the chip 60 and the surface 622 of the encapsulating material 62. The conductive trace 644 serves to electrically connect the build-up layer 64 and bond pads 604 of the chip 60. Thus, after a solder ball 66 is mounted on the build-up layer 64 and electrically connected to the conductive trace 644, the chip 60 is capable of electrically connecting the external devices via the solder ball 66.
The semiconductor package 6 can provide a larger area for distributing more input/output connections. However, the encapsulating material 62 is not formed on a high rigid substrate and the part for mounting the chip 60 is thinner than the part free of mounting the chip 60. Thus, warpage can be resulted during temperature cycling in subsequent processes. Further, a crack may be occurred in a position of a numeral 624 due to concentration of stresses. Delamination between the chip 60 and the encapsulating material may also be resulted due to the mismatch of coefficient of thermal expansion (CTE) between the encapsulating material 62 and the chip 60 encapsulated therein.
In the light of drawbacks of the foregoing U.S. Pat. No. 6,271,469, U.S. Pat. No. 6,498,387 has disclosed a semiconductor package having a glass for carrying chips. Referring to FIG. 8, in a semiconductor package 7, a chip 70 mounted on a glass 71 is encapsulated by being coated with an epoxy layer 72. A plurality of openings is provided on the epoxy layer 72 to expose bond pads 702 located on the chip 70. Then, a plurality of conductive traces 73 is provided on the epoxy layer 72 for electrically connecting the bond pads 702. Subsequently, a solder mask layer 74 is disposed on the epoxy layer 72 for covering the conductive traces 73 and then a plurality of openings is provided through the solder mask layer 74 to partially expose the conductive traces 73 for mounting solder balls 75.
The foregoing U.S. Pat. No. 6,498,387 uses the glass 71 for carrying the chip 70, by which the high rigidity of the glass 71 is capable of solving the problems in the U.S. Pat. No. 6,217,496, such as the warpage and crack caused by the encapsulating material. Also, as the glass 71 has a CTE close to that of the chip 70, the delamination caused by the mismatch of CTE can be eliminated. However, the chip 70 is mounted onto the glass 71, such that the semiconductor package 7 cannot meet the requirement of miniaturization as the total thickness of the entire package is the sum of the chip 70, the glass 71 and build-up layers disposed on the chip 70. Additionally, during temperature cycling in subsequent processes, thermal stresses may cause a crack in the chip 70 which is completely encapsulated by the epoxy layer 72 as the CTE for the chip 70 and the epoxy layer 72 may be mismatched. Further, external water vapors may accumulate on an active surface of the chip 70 via the epoxy layer 72 having high moisture absorption as both sides of the epoxy layer 72 are directly exposed in atmosphere. Therefore, a so-called ‘popcorn phenomenon’ would be resulted to thereby not enhancing the reliability of the products.
Accordingly, the semiconductor packages proposed in the U.S. Pat. Nos. 6,217,496 and 6,498,387 are inherent with significant problems which have to be solved.